ADDVL

Add multiple of vector register size to scalar register

Add the current vector register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer, and place the result in the 64-bit destination general-purpose register or current stack pointer.

Encoding: SVE

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	0	0	0	1						0	1	0	1	0
									op		Rn										imm6						Rd

ADDVL <Xd|SP>, <Xn|SP>, #<imm>

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer n = UInt(Rn);
constant integer d = UInt(Rd);
constant integer imm = SInt(imm6);

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant bits(64) operand1 = if n == 31 then SP[64] else X[n, 64];
constant bits(64) result = operand1 + (imm * (VL DIV 8));

if d == 31 then
    SP[64] = result;
else
    X[d, 64] = result;

Explanations

<Xd|SP>: Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.
<Xn|SP>: Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.
<imm>: Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.