ADR

Compute vector address

Optionally sign or zero-extend the least significant 32 bits of each element from a vector of offsets or indices in the second source vector, scale each index by 2, 4 or 8, add to a vector of base addresses from the first source vector, and place the resulting addresses in the destination vector. This instruction is unpredicated.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Encoding: Packed offsets

Variants: FEAT_SVE (PROFILE_A)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	0	1		1						1	0	1	0
									sz		Zm									msz		Zn					Zd

ADR <Zd>.<T>, [<Zn>.<T>, <Zm>.<T>{, <mod> <amount>}]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF);
constant integer esize = 32 << UInt(sz);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd);
constant integer osize = esize;
constant boolean unsigned = TRUE;
constant integer mbytes = 1 << UInt(msz);

Encoding: Unpacked 32-bit signed offsets

Variants: FEAT_SVE (PROFILE_A)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	0	0	0	1						1	0	1	0
								opc			Zm									msz		Zn					Zd

ADR <Zd>.D, [<Zn>.D, <Zm>.D, SXTW{<amount>}]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd);
constant integer osize = 32;
constant boolean unsigned = FALSE;
constant integer mbytes = 1 << UInt(msz);

Encoding: Unpacked 32-bit unsigned offsets

Variants: FEAT_SVE (PROFILE_A)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	0	0	1	1						1	0	1	0
								opc			Zm									msz		Zn					Zd

ADR <Zd>.D, [<Zn>.D, <Zm>.D, UXTW{<amount>}]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd);
constant integer osize = 32;
constant boolean unsigned = TRUE;
constant integer mbytes = 1 << UInt(msz);

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant bits(VL) base = Z[n, VL];
constant bits(VL) offs = Z[m, VL];
bits(VL) result;

for e = 0 to elements-1
    constant bits(esize) addr = Elem[base, e, esize];
    constant integer offset = Int(Elem[offs, e, esize], unsigned);
    Elem[result, e, esize] = addr + (offset * mbytes);

Z[d, VL] = result;

Explanations

<Zd>: Is the name of the destination scalable vector register, encoded in the "Zd" field.
<T>: <Zn>: Is the name of the base scalable vector register, encoded in the "Zn" field.
<Zm>: Is the name of the offset scalable vector register, encoded in the "Zm" field.
<mod>: <amount>:

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.