BCAX

Bit clear and exclusive-OR

This instruction performs a bitwise AND of the 128-bit vector in a source SIMD&FP register and the complement of the vector in another source SIMD&FP register, then performs a bitwise exclusive-OR of the resulting vector and the vector in a third source SIMD&FP register, and writes the result to the destination SIMD&FP register.

Encoding: Advanced SIMD

Variants: FEAT_SHA3 (ARMv8.2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	1	1	1	0	0	0	1						0
									Op0		Rm						Ra					Rn					Rd

BCAX <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B

Decoding algorithm

if !IsFeatureImplemented(FEAT_SHA3) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer a = UInt(Ra);

Operation

AArch64.CheckFPAdvSIMDEnabled();

constant bits(128) operand1 = V[m, 128];
constant bits(128) operand2 = V[n, 128];
constant bits(128) operand3 = V[a, 128];

V[d, 128] = operand2 EOR (operand1 AND NOT(operand3));

Explanations

<Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Vn>: Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>: Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
<Va>: Is the name of the third SIMD&FP source register, encoded in the "Ra" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.