BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2

8-bit floating-point convert to BFloat16 (vector)

This instruction converts each 8-bit floating-point element from the lower or upper half of the source vector to BFloat16 while downscaling the value, and places the results in the 16-bit elements of the destination vector. BF1CVTL and BF2CVTL convert the elements from the lower half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[5:0]) and 2-UInt(FPMR.LSCALE2[5:0]), respectively. BF1CVTL2 and BF2CVTL2 convert the elements from the upper half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[5:0]) and 2-UInt(FPMR.LSCALE2[5:0]), respectively.

The 8-bit floating-point encoding format for BF1CVTL and BF1CVTL2 is selected by FPMR.F8S1. The 8-bit floating-point encoding format for BF2CVTL and BF2CVTL2 is selected by FPMR.F8S2.

Encoding: Advanced SIMD

Variants: FEAT_FP8 (ARMv9.5)

313029282726252423222120191817161514131211109876543210
01011101x100001011110
QUsizeopcodeRnRd

BF1CVTL{2} (size == 10)

BF1CVTL{2} <Vd>.8H, <Vn>.<Ta>

BF2CVTL{2} (size == 11)

BF2CVTL{2} <Vd>.8H, <Vn>.<Ta>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer part = UInt(Q);
constant integer elements = 64 DIV 8;
constant boolean issrc2 = size == '11';

Operation

CheckFPMREnabled(); CheckFPAdvSIMDEnabled64();
constant bits(64) operand = Vpart[n, part, 64];
bits(128) result;

for e = 0 to elements-1
    Elem[result, e, 16] = FP8ConvertBF(Elem[operand, e, 8], issrc2, FPCR, FPMR);

V[d, 128] = result;

Explanations

2: <Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Vn>: Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<Ta>: