BFCLAMP

Multi-vector BFloat16 clamp to minimum/maximum number

This instruction clamps each BFloat16 element in the two or four destination vectors to between the BFloat16 minimum value in the corresponding element of the first source vector and the BFloat16 maximum value in the corresponding element of the second source vector and destructively places the clamped results in the corresponding elements of the two or four destination vectors.

Regardless of the value of FPCR.AH, the behavior is as follows for each minimum number and maximum number operation:

  • Negative zero compares less than positive zero.
  • If one value is numeric and the other is a quiet NaN, the result is the numeric value.
  • When FPCR.DN is 0, if either value is a signaling NaN or if both values are NaNs, the result is a quiet NaN.
  • When FPCR.DN is 1, if either value is a signaling NaN or if both values are NaNs, the result is Default NaN.

    • This instruction follows SME2 non-widening BFloat16 numerical behaviors corresponding to instructions that place their results in two or four SVE Z vectors.

    This instruction is unpredicated.

    ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.

    Encoding: Two registers

    Variants: FEAT_SME2 && FEAT_SVE_B16B16 (FEAT_SME2 && FEAT_SVE_B16B16)

    313029282726252423222120191817161514131211109876543210
    110000010011100000
    sizeZmZnZdop

    BFCLAMP { <Zd1>.H-<Zd2>.H }, <Zn>.H, <Zm>.H

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_SVE_B16B16) then
    EndOfDecode(Decode_UNDEF);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd:'0');
constant integer nreg = 2;

    Encoding: Four registers

    Variants: FEAT_SME2 && FEAT_SVE_B16B16 (FEAT_SME2 && FEAT_SVE_B16B16)

    313029282726252423222120191817161514131211109876543210
    1100000100111001000
    sizeZmZnZdop

    BFCLAMP { <Zd1>.H-<Zd4>.H }, <Zn>.H, <Zm>.H

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_SVE_B16B16) then
    EndOfDecode(Decode_UNDEF);
constant integer n = UInt(Zn);
constant integer m = UInt(Zm);
constant integer d = UInt(Zd:'00');
constant integer nreg = 4;

    Operation

    CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV 16;
array [0..3] of bits(VL) results;

for r = 0 to nreg-1
    constant bits(VL) operand1 = Z[n, VL];
    constant bits(VL) operand2 = Z[m, VL];
    constant bits(VL) operand3 = Z[d+r, VL];
    for e = 0 to elements-1
        constant bits(16) element1 = Elem[operand1, e, 16];
        constant bits(16) element2 = Elem[operand2, e, 16];
        constant bits(16) element3 = Elem[operand3, e, 16];
        constant bits(16) maxelement = BFMaxNum(element1, element3, FPCR);
        Elem[results[r], e, 16] = BFMinNum(maxelement, element2, FPCR);

for r = 0 to nreg-1
    Z[d+r, VL] = results[r];

    Explanations

    <Zd1>: For the "Two registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.
    <Zd1>: For the "Four registers" variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.
    <Zd2>: Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.
    <Zn>: Is the name of the first source scalable vector register, encoded in the "Zn" field.
    <Zm>: Is the name of the second source scalable vector register, encoded in the "Zm" field.
    <Zd4>: Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.