BFMAX (multiple vectors)

Multi-vector BFloat16 maximum

This instruction determines the maximum of BFloat16 elements of the two or four second source vectors and the corresponding BFloat16 elements of the two or four first source vectors and destructively places the results in the corresponding elements of the two or four first source vectors.

When FPCR.AH is 0, the behavior is as follows:

  • Negative zero compares less than positive zero.
  • When FPCR.DN is 0, if either element is a NaN, the result is a quiet NaN.
  • When FPCR.DN is 1, if either element is a NaN, the result is Default NaN.

    • When FPCR.AH is 1, the behavior is as follows:

  • If both elements are zeros, regardless of the sign of either zero, the result is the second element.
  • If either element is a NaN, regardless of the value of FPCR.DN, the result is the second element.

    • This instruction follows SME2 non-widening BFloat16 numerical behaviors corresponding to instructions that place their results in two or four SVE Z vectors.

    This instruction is unpredicated.

    ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.

    Encoding: Two registers

    Variants: FEAT_SME2 && FEAT_SVE_B16B16 (FEAT_SME2 && FEAT_SVE_B16B16)

    313029282726252423222120191817161514131211109876543210
    110000010010101100010000
    sizeZmopcZdno2

    BFMAX { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H }, { <Zm1>.H-<Zm2>.H }

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_SVE_B16B16) then
    EndOfDecode(Decode_UNDEF);
constant integer dn = UInt(Zdn:'0');
constant integer m = UInt(Zm:'0');
constant integer nreg = 2;

    Encoding: Four registers

    Variants: FEAT_SME2 && FEAT_SVE_B16B16 (FEAT_SME2 && FEAT_SVE_B16B16)

    313029282726252423222120191817161514131211109876543210
    11000001001001011100100000
    sizeZmopcZdno2

    BFMAX { <Zdn1>.H-<Zdn4>.H }, { <Zdn1>.H-<Zdn4>.H }, { <Zm1>.H-<Zm4>.H }

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_SVE_B16B16) then
    EndOfDecode(Decode_UNDEF);
constant integer dn = UInt(Zdn:'00');
constant integer m = UInt(Zm:'00');
constant integer nreg = 4;

    Operation

    CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV 16;
array [0..3] of bits(VL) results;

for r = 0 to nreg-1
    constant bits(VL) operand1 = Z[dn+r, VL];
    constant bits(VL) operand2 = Z[m+r, VL];
    for e = 0 to elements-1
        constant bits(16) element1 = Elem[operand1, e, 16];
        constant bits(16) element2 = Elem[operand2, e, 16];
        Elem[results[r], e, 16] = BFMax(element1, element2, FPCR);

for r = 0 to nreg-1
    Z[dn+r, VL] = results[r];

    Explanations

    <Zdn1>: For the "Two registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2.
    <Zdn1>: For the "Four registers" variant: is the name of the first scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4.
    <Zdn2>: Is the name of the second scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 2 plus 1.
    <Zm1>: For the "Two registers" variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 2.
    <Zm1>: For the "Four registers" variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 4.
    <Zm2>: Is the name of the second scalable vector register of the second source multi-vector group, encoded as "Zm" times 2 plus 1.
    <Zdn4>: Is the name of the fourth scalable vector register of the destination and first source multi-vector group, encoded as "Zdn" times 4 plus 3.
    <Zm4>: Is the name of the fourth scalable vector register of the second source multi-vector group, encoded as "Zm" times 4 plus 3.