BFMIN

BFloat16 minimum (predicated)

Determine the minimum of active BFloat16 elements of the second source vector and corresponding BFloat16 elements of the first source vector and destructively place the results in the corresponding elements of the first source vector.

When FPCR.AH is 0, the behavior is as follows:

Negative zero compares less than positive zero.

When FPCR.DN is 0, if either element is a NaN, the result is a quiet NaN.

When FPCR.DN is 1, if either element is a NaN, the result is Default NaN.

When FPCR.AH is 1, the behavior is as follows:

If both elements are zeros, regardless of the sign of either zero, the result is the second element.

If either element is a NaN, regardless of the value of FPCR.DN, the result is the second element.

Inactive elements in the destination vector register remain unmodified.

This instruction follows SVE2 non-widening BFloat16 numerical behaviors.

ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.

Encoding: SVE2

Variants: FEAT_SVE_B16B16 (ARMv9.4)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	0	0	0	0	0	1	1	1	1	0	0
								size				opc							Pg			Zm					Zdn

BFMIN <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE_B16B16) then EndOfDecode(Decode_UNDEF);

constant integer g = UInt(Pg);
constant integer dn = UInt(Zdn);
constant integer m = UInt(Zm);

Operation

if IsFeatureImplemented(FEAT_SME2) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV 16;
constant bits(PL) mask = P[g, PL];
constant bits(VL) operand1 = Z[dn, VL];
constant bits(VL) operand2 = if AnyActiveElement(mask, 16) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    constant bits(16) element1 = Elem[operand1, e, 16];
    if ActivePredicateElement(mask, e, 16) then
        constant bits(16) element2 = Elem[operand2, e, 16];
        Elem[result, e, 16] = BFMin(element1, element2, FPCR);
    else
        Elem[result, e, 16] = element1;

Z[dn, VL] = result;

Explanations

<Zdn>: Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.
<Pg>: Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Zm>: Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operational Notes

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:

• The MOVPRFX can be predicated or unpredicated.
• A predicated MOVPRFX must use the same governing predicate register as this instruction.
• A predicated MOVPRFX must use the larger of the destination element size and first source element size in the preferred disassembly of this instruction.
• The MOVPRFX must specify the same destination register as this instruction.
• The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.