BFMLALB, BFMLALT (vector)

BFloat16 floating-point widening multiply-add long (vector)

This instruction widens the even-numbered (bottom) or odd-numbered (top) 16-bit elements in the first and second source vectors from Bfloat16 to single-precision format. The instruction then multiplies and adds these values without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding BFloat16 elements in the source vectors.

ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.

Encoding: Vector

Variants: FEAT_BF16 (ARMv8.6)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		1	0	1	1	1	0	1	1	0						1	1	1	1	1	1
	Q	U						size			Rm						opcode					Rn					Rd

BFMLAL<bt> <Vd>.4S, <Vn>.8H, <Vm>.8H

Decoding algorithm

if !IsFeatureImplemented(FEAT_BF16) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);

constant integer elements = 128 DIV 32;
constant integer sel = UInt(Q);

Operation

CheckFPAdvSIMDEnabled64();
constant bits(128) operand1 = V[n, 128];
constant bits(128) operand2 = V[m, 128];
constant bits(128) operand3 = V[d, 128];
bits(128) result;

for e = 0 to elements-1
    constant bits(16) element1 = Elem[operand1, 2 * e + sel, 16];
    constant bits(16) element2 = Elem[operand2, 2 * e + sel, 16];
    constant bits(32) addend   = Elem[operand3, e, 32];
    Elem[result, e, 32] = BFMulAddH(addend, element1, element2, FPCR);

V[d, 128] = result;

Explanations

<bt>: <Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Vn>: Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>: Is the name of the second SIMD&FP source register, encoded in the "Rm" field.