CMPLO (vectors)
Compare unsigned lower than vector, setting the condition flags
Compare active unsigned integer elements in the
first source vector being lower than corresponding unsigned elements in the second source vector, and
place the boolean results of the
comparison in the corresponding elements of the destination
predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C)
condition flags based on the predicate result,
and the V flag to zero.
Encoding: Higher
Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | | | 0 | | | | | | 0 | 0 | 0 | | | | | | | | | 1 | | | | |
| | | size | | Zm | op | | o2 | Pg | Zn | ne | Pd |
---|
CMPLO <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
Equivalent to: CMPHI <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
Explanations
<Pd>:
Is the name of the destination scalable predicate register, encoded in the "Pd" field.<T>:
<Pg>:
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.<Zm>:
Is the name of the second source scalable vector register, encoded in the "Zm" field.<Zn>:
Is the name of the first source scalable vector register, encoded in the "Zn" field.Operational Notes
If PSTATE.DIT is 1:
-
The execution time of this instruction is independent of:
-
The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
-
The values of the NZCV flags.
-
The response of this instruction to asynchronous exceptions does not vary based on:
-
The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
-
The values of the NZCV flags.
If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.