CMPP

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This instruction subtracts the 56-bit address held in the second source register from the 56-bit address held in the first source register, updates the condition flags based on the result of the subtraction, and discards the result.

Encoding: Integer

Variants: FEAT_MTE (ARMv8.5)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	1	1	0	1	0	1	1	0						0	0	0	0	0	0						1	1	1	1	1
sf		S									Rm					opcode						Rn					Rd

CMPP <Xn|SP>, <Xm|SP>

Equivalent to: SUBPS XZR, <Xn|SP>, <Xm|SP>

Explanations

<Xn|SP>: Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.
<Xm|SP>: Is the 64-bit name of the second general-purpose source register or stack pointer, encoded in the "Rm" field.