DMB

Data memory barrier

This instruction is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier.

Encoding: System

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	0	0	0	0	0	1	1	0	0	1	1					1	0	1	1	1	1	1	1
																				CRm					opc		Rt

DMB (#<imm> syntax. All unsupported and reserved options must execute as a full system barrier operation, but software must not rely on this behavior. For more information on whether an access is before or after a barrier instruction, see x[Data Memory Barrier (DMB)](BEIIECBH) or see x[Data Synchronization Barrier (DSB)](BEICEFJH)." class="text-blue-400 hover:text-yellow-300"><option>|#<imm>)

Decoding algorithm

MBReqDomain domain;
MBReqTypes types;
case CRm<3:2> of
    when '00' domain = MBReqDomain_OuterShareable;
    when '01' domain = MBReqDomain_Nonshareable;
    when '10' domain = MBReqDomain_InnerShareable;
    when '11' domain = MBReqDomain_FullSystem;
case CRm<1:0> of
    when '00' types = MBReqTypes_All; domain = MBReqDomain_FullSystem;
    when '01' types = MBReqTypes_Reads;
    when '10' types = MBReqTypes_Writes;
    when '11' types = MBReqTypes_All;

Operation

DataMemoryBarrier(domain, types);

Explanations

<option>: <imm>: Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field.