Three-way exclusive-OR
This instruction performs a three-way exclusive-OR of the values in the three source SIMD&FP registers, and writes the result to the destination SIMD&FP register.
Variants: FEAT_SHA3 (ARMv8.2)
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||
Op0 | Rm | Ra | Rn | Rd |
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EOR3 <Vd>.16B, <Vn>.16B, <Vm>.16B, <Va>.16B
if !IsFeatureImplemented(FEAT_SHA3) then EndOfDecode(Decode_UNDEF); constant integer d = UInt(Rd); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer a = UInt(Ra);
AArch64.CheckFPAdvSIMDEnabled(); constant bits(128) operand1 = V[m, 128]; constant bits(128) operand2 = V[n, 128]; constant bits(128) operand3 = V[a, 128]; V[d, 128] = operand2 EOR operand1 EOR operand3;
If PSTATE.DIT is 1: