EOR3

Bitwise exclusive-OR of three vectors

Bitwise exclusive-OR the corresponding elements of all three source vectors, and destructively place the results in the corresponding elements of the destination and first source vector. This instruction is unpredicated.

Encoding: SVE2

Variants: FEAT_SVE2 || FEAT_SME (FEAT_SVE2 || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	0	0	0	1						0	0	1	1	1	0
								opc			Zm										o2	Zk					Zdn

EOR3 <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer m = UInt(Zm);
constant integer k = UInt(Zk);
constant integer dn = UInt(Zdn);

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant bits(VL) operand1 = Z[dn, VL];
constant bits(VL) operand2 = Z[m, VL];
constant bits(VL) operand3 = Z[k, VL];

Z[dn, VL] = operand1 EOR operand2 EOR operand3;

Explanations

<Zdn>: Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.
<Zm>: Is the name of the second source scalable vector register, encoded in the "Zm" field.
<Zk>: Is the name of the third source scalable vector register, encoded in the "Zk" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:

• The MOVPRFX must be unpredicated.
• The MOVPRFX must specify the same destination register as this instruction.
• The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.