EXPAND

Copy lower-numbered vector elements to active elements

In order of increasing element number, unpack consecutive elements from the source vector into increasing active elements of the destination vector, setting any inactive elements to zero.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled, or FEAT_SME2p2 is implemented.

Encoding: SVE2

Variants: FEAT_SVE2p2 || FEAT_SME2p2 (FEAT_SVE2p2 || FEAT_SME2p2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1			1	1	0	0	0	1	1	0	0
								size											Pg			Zn					Zd

EXPAND <Zd>.<T>, <Pg>, <Zn>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 8 << UInt(size);
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);

Operation

if IsFeatureImplemented(FEAT_SME2p2) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant bits(PL) mask = P[g, PL];
constant bits(VL) operand1 = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result;
integer x = 0;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        Elem[result, e, esize] = Elem[operand1, x, esize];
        x = x + 1;
    else
        Elem[result, e, esize] = Zeros(esize);

Z[d, VL] = result;

Explanations

<Zd>: Is the name of the destination scalable vector register, encoded in the "Zd" field.
<T>: <Pg>: Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Zn>: Is the name of the source scalable vector register, encoded in the "Zn" field.