F1CVTLT, F2CVTLT

8-bit floating-point convert to half-precision (top)

Convert each odd-numbered 8-bit floating-point element of the source vector to half-precision while downscaling the value, and place the results in the overlapping 16-bit elements of the destination vector. F1CVTLT scales the values by 2-UInt(FPMR.LSCALE[3:0]). F2CVTLT scales the values by 2-UInt(FPMR.LSCALE2[3:0]).

The 8-bit floating-point encoding format for F1CVTLT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVTLT is selected by FPMR.F8S2.

This instruction is unpredicated.

Encoding: F1CVTLT

Variants: (FEAT_SVE2 || FEAT_SME2) && FEAT_FP8 ((FEAT_SVE2 || FEAT_SME2) && FEAT_FP8)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	0	0	0	0	1	0	0	1	0	0	1	1	0	0
															L					opc		Zn					Zd

F1CVTLT <Zd>.H, <Zn>.B

Decoding algorithm

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) ||
      !IsFeatureImplemented(FEAT_FP8)) then EndOfDecode(Decode_UNDEF);
constant integer esize = 16;
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant boolean issrc2 = FALSE;

Encoding: F2CVTLT

Variants: (FEAT_SVE2 || FEAT_SME2) && FEAT_FP8 ((FEAT_SVE2 || FEAT_SME2) && FEAT_FP8)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	0	0	0	0	1	0	0	1	0	0	1	1	0	1
															L					opc		Zn					Zd

F2CVTLT <Zd>.H, <Zn>.B

Decoding algorithm

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) ||
      !IsFeatureImplemented(FEAT_FP8)) then EndOfDecode(Decode_UNDEF);
constant integer esize = 16;
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant boolean issrc2 = TRUE;

Operation

CheckFPMREnabled();
if IsFeatureImplemented(FEAT_SME2) then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant bits(VL) operand = Z[n, VL];
bits(VL) result;
for e = 0 to elements-1
    constant bits(esize DIV 2) element = Elem[operand, 2*e + 1, esize DIV 2];
    Elem[result, e, esize] = FP8ConvertFP(element, issrc2, FPCR, FPMR);

Z[d, VL] = result;

Explanations

<Zd>: Is the name of the destination scalable vector register, encoded in the "Zd" field.
<Zn>: Is the name of the source scalable vector register, encoded in the "Zn" field.