FAMIN

Floating-point absolute minimum

This instruction determines the minimum absolute value from floating-point elements of the first source vector and the corresponding floating-point elements of the second source vector, and places the results in the corresponding elements of the destination vector.

Regardless of the value of FPCR.AH, the behavior is as follows:

When FPCR.DN is 0, if either element is a NaN, the result is a quiet NaN.

When FPCR.DN is 1, if either element is a NaN, the result is the Default NaN, with the sign bit set to 0.

Denormalized inputs and results are never flushed to zero, as if FPCR.{FZ, FZ16, FIZ} are all 0.

Denormalized inputs never generate an Input Denormal floating-point exception.

Encoding: Half-precision

Variants: FEAT_AdvSIMD && FEAT_FAMINMAX (FEAT_AdvSIMD && FEAT_FAMINMAX)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		1	0	1	1	1	0	1	1	0						0	0	0	1	1	1
	Q	U						a			Rm							opcode				Rn					Rd

FAMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FAMINMAX) then
    EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 16;
constant integer datasize = if Q == '1' then 128 else 64;
constant integer elements = datasize DIV esize;

Encoding: Single-precision and double-precision

Variants: FEAT_AdvSIMD && FEAT_FAMINMAX (FEAT_AdvSIMD && FEAT_FAMINMAX)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		1	0	1	1	1	0	1	x	1						1	1	0	1	1	1
	Q	U						size			Rm					opcode						Rn					Rd

FAMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FAMINMAX) then
    EndOfDecode(Decode_UNDEF);
if Q == '0' && size == '11' then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 8 << UInt(size);
constant integer datasize = if Q == '1' then 128 else 64;
constant integer elements = datasize DIV esize;

Operation

CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand1 = V[n, datasize];
constant bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;

for e = 0 to elements-1
    constant bits(esize) op1 = Elem[operand1, e, esize];
    constant bits(esize) op2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAbsMin(op1, op2, FPCR);
V[d, datasize] = result;

Explanations

<Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>: <T>: <Vn>: Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>: Is the name of the second SIMD&FP source register, encoded in the "Rm" field.