FCSEL

Floating-point conditional select (scalar)

This instruction allows the SIMD&FP destination register to take the value from either one or the other of two SIMD&FP source registers. If the condition passes, the first SIMD&FP source register value is taken, otherwise the second SIMD&FP source register value is taken.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Floating-point

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	1	1	1	1	0			1										1	1
M		S						ftype			Rm					cond						Rn					Rd

Half-precision (ftype == 11)

FCSEL <Hd>, <Hn>, <Hm>, <cond>

Single-precision (ftype == 00)

FCSEL <Sd>, <Sn>, <Sm>, <cond>

Double-precision (ftype == 01)

FCSEL <Dd>, <Dn>, <Dm>, <cond>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF);
if ftype == '10' then EndOfDecode(Decode_UNDEF);
if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF);

constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);

constant integer datasize = 8 << UInt(ftype EOR '10');
constant bits(4) condition = cond;

Operation

CheckFPEnabled64();
bits(datasize) result;

constant boolean condition_holds = ConditionHolds(condition);
result = if condition_holds then V[n, datasize] else V[m, datasize];

V[d, datasize] = result;

Explanations

<Hd>: Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>: Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
<Hm>: Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
<cond>: <Sd>: Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Sn>: Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
<Sm>: Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
<Dd>: Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Dn>: Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
<Dm>: Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.