FCVT

Floating-point convert precision (scalar)

This instruction converts the floating-point value in the SIMD&FP source register to the precision for the destination register data type using the rounding mode that is determined by the FPCR and writes the result to the SIMD&FP destination register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Floating-point

Variants: FEAT_FP (ARMv8.0)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	1	1	1	1	0			1	0	0	0	1			1	0	0	0	0
M		S						ftype							opc							Rn					Rd

Half-precision to single-precision (ftype == 11 && opc == 00)

FCVT <Sd>, <Hn>

Half-precision to double-precision (ftype == 11 && opc == 01)

FCVT <Dd>, <Hn>

Single-precision to half-precision (ftype == 00 && opc == 11)

FCVT <Hd>, <Sn>

Single-precision to double-precision (ftype == 00 && opc == 01)

FCVT <Dd>, <Sn>

Double-precision to half-precision (ftype == 01 && opc == 11)

FCVT <Hd>, <Dn>

Double-precision to single-precision (ftype == 01 && opc == 00)

FCVT <Sd>, <Dn>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF);
if ftype == opc || ftype == '10' || opc == '10' then EndOfDecode(Decode_UNDEF);

constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer srcsize = 8 << UInt(ftype EOR '10');
constant integer dstsize = 8 << UInt(opc EOR '10');

Operation

CheckFPEnabled64();

constant bits(srcsize) operand = V[n, srcsize];
bits(128) result = if IsMerging(FPCR) then V[d, 128] else Zeros(128);

Elem[result, 0, dstsize] = FPConvert(operand, FPCR, dstsize);

V[d, 128] = result;

Explanations

<Sd>: Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>: Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Dd>: Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hd>: Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Sn>: Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Dn>: Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.