FCVTAU (scalar SIMD&FP)

Floating-point convert to unsigned integer, rounding to nearest with ties to away (scalar SIMD&FP)

This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Floating-point

Variants: FEAT_FPRCVT (ARMv9.6)

313029282726252423222120191817161514131211109876543210
0011110111011000000
sfSftypermodeopcodeRnRd

Half-precision to 32-bit (sf == 0 && ftype == 11)

FCVTAU <Sd>, <Hn>

Half-precision to 64-bit (sf == 1 && ftype == 11)

FCVTAU <Dd>, <Hn>

Single-precision to 64-bit (sf == 1 && ftype == 00)

FCVTAU <Dd>, <Sn>

Double-precision to 32-bit (sf == 0 && ftype == 01)

FCVTAU <Sd>, <Dn>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FPRCVT) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);

constant integer intsize = 32 << UInt(sf);
constant integer fltsize = 8 << UInt(ftype EOR '10');

Operation

CheckFPEnabled64();

bits(fltsize) fltval;
bits(intsize) intval;
constant boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);

fltval = V[n, fltsize];
intval = FPToFixed(fltval, 0, TRUE, FPCR, FPRounding_TIEAWAY, intsize);
Elem[result, 0, intsize] = intval;

V[d, 128] = result;

Explanations

<Sd>: Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>: Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Dd>: Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Sn>: Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Dn>: Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.