FCVTL

Multi-vector convert from half-precision to deinterleaved single-precision

This instruction converts each element of the source vector from half-precision to single-precision floating-point, and places the two-way deinterleaved results in the double-width destination elements of the destination vectors.

This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.

This instruction is unpredicated.

ID_AA64SMFR0_EL1.F16F16 indicates whether this instruction is implemented.

Encoding: SME2

Variants: FEAT_SME_F16F16 (ARMv9.4)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	0	0	0	0	1	1	0	1	0	0	0	0	0	1	1	1	0	0	0										1
																						Zn					Zd				L

FCVTL { <Zd1>.S-<Zd2>.S }, <Zn>.H

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME_F16F16) then EndOfDecode(Decode_UNDEF);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd:'0');

Operation

CheckStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer pairs = VL DIV 32;
constant bits(VL) operand = Z[n, VL];
bits(VL) result0;
bits(VL) result1;

for p = 0 to pairs-1
    constant bits(16) element1 = Elem[operand, 2*p+0, 16];
    constant bits(16) element2 = Elem[operand, 2*p+1, 16];
    constant bits(32) res1 = FPConvertSVE(element1, FPCR, 32);
    constant bits(32) res2 = FPConvertSVE(element2, FPCR, 32);
    Elem[result0, p, 32] = res1;
    Elem[result1, p, 32] = res2;

Z[d+0, VL] = result0;
Z[d+1, VL] = result1;

Explanations

<Zd1>: Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.
<Zd2>: Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.
<Zn>: Is the name of the source scalable vector register, encoded in the "Zn" field.