FCVTN (half-precision to 8-bit floating-point)

Half-precision to 8-bit floating-point convert and narrow (vector)

This instruction converts half-precision elements of the two source vectors to 8-bit floating-point while scaling the values by 2SInt(FPMR.NSCALE[4:0]), and places the in-order results in the 8-bit elements of the destination vector.

The 8-bit floating-point encoding format is selected by FPMR.F8D.

Encoding: Advanced SIMD

Variants: FEAT_FP8 (ARMv9.5)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		0	0	1	1	1	0	0	1	0						1	1	1	1	0	1
	Q	U						size			Rm						opcode					Rn					Rd

FCVTN <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer datasize = if Q == '1' then 128 else 64;
constant integer elements = datasize DIV 16;

Operation

CheckFPMREnabled(); CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand1 = V[n, datasize];
constant bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;

for e = 0 to elements-1
    Elem[result, 0*elements + e, 8] = FPConvertFP8(Elem[operand1, e, 16], FPCR, FPMR, 8);
    Elem[result, 1*elements + e, 8] = FPConvertFP8(Elem[operand2, e, 16], FPCR, FPMR, 8);

V[d, datasize] = result;

Explanations

<Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Ta>: <Vn>: Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Tb>: <Vm>: Is the name of the second SIMD&FP source register, encoded in the "Rm" field.