FCVTN, FCVTN2 (single-precision to 8-bit floating-point)

Single-precision to 8-bit floating-point convert and narrow (vector)

This instruction converts each single-precision element of the two source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE), and places the in-order results in the 8-bit elements of the lower or upper half of the destination vector. FCVTN writes the results to the lower half of the destination vector and clears the upper half. FCVTN2 writes the results to the upper half of the destination vector without affecting the other bits of the vector.

The 8-bit floating-point encoding format is selected by FPMR.F8D.

Encoding: Advanced SIMD

Variants: FEAT_FP8 (ARMv9.5)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		0	0	1	1	1	0	0	0	0						1	1	1	1	0	1
	Q	U						size			Rm						opcode					Rn					Rd

FCVTN{2} <Vd>.<Ta>, <Vn>.4S, <Vm>.4S

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer part = UInt(Q);
constant integer elements = 128 DIV 32;

Operation

CheckFPMREnabled(); CheckFPAdvSIMDEnabled64();
constant bits(128) operand1 = V[n, 128];
constant bits(128) operand2 = V[m, 128];
bits(64) result;

for e = 0 to elements-1
    Elem[result, 0*elements + e, 8] = FPConvertFP8(Elem[operand1, e, 32], FPCR, FPMR, 8);
    Elem[result, 1*elements + e, 8] = FPConvertFP8(Elem[operand2, e, 32], FPCR, FPMR, 8);

Vpart[d, part, 64] = result;

Explanations

2: <Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Ta>: <Vn>: Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>: Is the name of the second SIMD&FP source register, encoded in the "Rm" field.