FCVTZU

Floating-point convert to unsigned integer, rounding toward zero (predicated)

Convert to the unsigned integer nearer to zero from each active floating-point element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified or are set to zero, depending on whether merging or zeroing predication is selected.

If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.

Encoding: Half-precision to 16-bit, merging

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	0	1	0	1	1	0	1	1	1	0	1
								opc					opc2		int_U				Pg			Zn					Zd

FCVTZU <Zd>.H, <Pg>/M, <Zn>.H

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 16;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 16;
constant integer d_esize = 16;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = TRUE;

Encoding: Half-precision to 16-bit, zeroing

Variants: FEAT_SVE2p2 || FEAT_SME2p2 (FEAT_SVE2p2 || FEAT_SME2p2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	0	0	1	0	1	1	1	1	0	1	1	1
								opc							o2		o3	int_U	Pg			Zn					Zd

FCVTZU <Zd>.H, <Pg>/Z, <Zn>.H

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 16;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 16;
constant integer d_esize = 16;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = FALSE;

Encoding: Half-precision to 32-bit, merging

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	0	1	0	1	1	1	0	1	1	0	1
								opc					opc2		int_U				Pg			Zn					Zd

FCVTZU <Zd>.S, <Pg>/M, <Zn>.H

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 32;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 16;
constant integer d_esize = 32;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = TRUE;

Encoding: Half-precision to 32-bit, zeroing

Variants: FEAT_SVE2p2 || FEAT_SME2p2 (FEAT_SVE2p2 || FEAT_SME2p2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	0	0	1	0	1	1	1	1	1	1	0	1
								opc							o2		o3	int_U	Pg			Zn					Zd

FCVTZU <Zd>.S, <Pg>/Z, <Zn>.H

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 32;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 16;
constant integer d_esize = 32;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = FALSE;

Encoding: Half-precision to 64-bit, merging

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	0	1	0	1	1	1	1	1	1	0	1
								opc					opc2		int_U				Pg			Zn					Zd

FCVTZU <Zd>.D, <Pg>/M, <Zn>.H

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 16;
constant integer d_esize = 64;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = TRUE;

Encoding: Half-precision to 64-bit, zeroing

Variants: FEAT_SVE2p2 || FEAT_SME2p2 (FEAT_SVE2p2 || FEAT_SME2p2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	0	0	1	0	1	1	1	1	1	1	1	1
								opc							o2		o3	int_U	Pg			Zn					Zd

FCVTZU <Zd>.D, <Pg>/Z, <Zn>.H

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 16;
constant integer d_esize = 64;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = FALSE;

Encoding: Single-precision to 32-bit, merging

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	1	0	0	1	1	1	0	1	1	0	1
								opc					opc2		int_U				Pg			Zn					Zd

FCVTZU <Zd>.S, <Pg>/M, <Zn>.S

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 32;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 32;
constant integer d_esize = 32;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = TRUE;

Encoding: Single-precision to 32-bit, zeroing

Variants: FEAT_SVE2p2 || FEAT_SME2p2 (FEAT_SVE2p2 || FEAT_SME2p2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	0	1	0	0	1	1	1	1	1	1	0	1
								opc							o2		o3	int_U	Pg			Zn					Zd

FCVTZU <Zd>.S, <Pg>/Z, <Zn>.S

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 32;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 32;
constant integer d_esize = 32;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = FALSE;

Encoding: Single-precision to 64-bit, merging

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	1	1	0	1	1	1	0	1	1	0	1
								opc					opc2		int_U				Pg			Zn					Zd

FCVTZU <Zd>.D, <Pg>/M, <Zn>.S

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 32;
constant integer d_esize = 64;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = TRUE;

Encoding: Single-precision to 64-bit, zeroing

Variants: FEAT_SVE2p2 || FEAT_SME2p2 (FEAT_SVE2p2 || FEAT_SME2p2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	0	1	1	0	1	1	1	1	1	1	0	1
								opc							o2		o3	int_U	Pg			Zn					Zd

FCVTZU <Zd>.D, <Pg>/Z, <Zn>.S

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 32;
constant integer d_esize = 64;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = FALSE;

Encoding: Double-precision to 32-bit, merging

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	1	1	0	1	1	0	0	1	1	0	1
								opc					opc2		int_U				Pg			Zn					Zd

FCVTZU <Zd>.S, <Pg>/M, <Zn>.D

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 64;
constant integer d_esize = 32;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = TRUE;

Encoding: Double-precision to 32-bit, zeroing

Variants: FEAT_SVE2p2 || FEAT_SME2p2 (FEAT_SVE2p2 || FEAT_SME2p2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	0	1	1	0	1	1	1	1	0	1	0	1
								opc							o2		o3	int_U	Pg			Zn					Zd

FCVTZU <Zd>.S, <Pg>/Z, <Zn>.D

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 64;
constant integer d_esize = 32;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = FALSE;

Encoding: Double-precision to 64-bit, merging

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	1	1	0	1	1	1	1	1	1	0	1
								opc					opc2		int_U				Pg			Zn					Zd

FCVTZU <Zd>.D, <Pg>/M, <Zn>.D

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 64;
constant integer d_esize = 64;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = TRUE;

Encoding: Double-precision to 64-bit, zeroing

Variants: FEAT_SVE2p2 || FEAT_SME2p2 (FEAT_SVE2p2 || FEAT_SME2p2)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	0	1	1	0	1	1	1	1	1	1	1	1
								opc							o2		o3	int_U	Pg			Zn					Zd

FCVTZU <Zd>.D, <Pg>/Z, <Zn>.D

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2p2) && !IsFeatureImplemented(FEAT_SME2p2) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 64;
constant integer g = UInt(Pg);
constant integer n = UInt(Zn);
constant integer d = UInt(Zd);
constant integer s_esize = 64;
constant integer d_esize = 64;
constant boolean unsigned = TRUE;
constant FPRounding rounding = FPRounding_ZERO;
constant boolean merging = FALSE;

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant bits(PL) mask = P[g, PL];
constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = if merging then Z[d, VL] else Zeros(VL);

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        constant bits(esize) element = Elem[operand, e, esize];
        constant bits(d_esize) res = FPToFixed(element, 0, unsigned, FPCR, rounding,
                                               d_esize);
        Elem[result, e, esize] = Extend(res, esize, unsigned);

Z[d, VL] = result;

Explanations

<Zd>: Is the name of the destination scalable vector register, encoded in the "Zd" field.
<Pg>: Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Zn>: Is the name of the source scalable vector register, encoded in the "Zn" field.

Operational Notes

The merging variant of this instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and the merging variant of this instruction is CONSTRAINED UNPREDICTABLE:

• The MOVPRFX can be predicated or unpredicated.
• A predicated MOVPRFX must use the same governing predicate register as the merging variant this instruction.
• A predicated MOVPRFX must use the larger of the destination element size and first source element size in the preferred disassembly of the merging variant of this instruction.
• The MOVPRFX must specify the same destination register as the merging variant of this instruction.
• The destination register must not refer to architectural register state referenced by any other source operand register of the merging variant of this instruction.