FJCVTZS

Floating-point Javascript convert to signed fixed-point, rounding toward zero

This instruction converts the double-precision floating-point value in the SIMD&FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. If the result is too large to be represented as a signed 32-bit integer, then the result is the integer modulo 232, as held in a 32-bit signed integer.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Double-precision to 32-bit

Variants: FEAT_JSCVT (ARMv8.3)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	1	1	1	1	0	0	1	1	1	1	1	1	0	0	0	0	0	0	0
sf		S						ftype			rmode		opcode									Rn					Rd

FJCVTZS <Wd>, <Dn>

Decoding algorithm

if !IsFeatureImplemented(FEAT_JSCVT) then EndOfDecode(Decode_UNDEF);

constant integer d = UInt(Rd);
constant integer n = UInt(Rn);

constant integer intsize = 32;
constant integer fltsize = 64;

Operation

CheckFPAdvSIMDEnabled64();
constant bits(fltsize) fltval = V[n, fltsize];

bits(intsize) intval;
bit z;
(intval, z) = FPToFixedJS(fltval, FPCR, intsize);

X[d, intsize] = intval;
PSTATE. = '0':z:'00';

Explanations

<Wd>: Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.
<Dn>: Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.