FMAX (scalar)

Floating-point maximum (scalar)

This instruction compares the two source SIMD&FP registers, and writes the larger of the two floating-point values to the destination SIMD&FP register.

When FPCR.AH is 0, the behavior is as follows:

  • Negative zero compares less than positive zero.
  • When FPCR.DN is 0, if either value is a NaN, the result is a quiet NaN.
  • When FPCR.DN is 1, if either value is a NaN, the result is Default NaN.

    • When FPCR.AH is 1, the behavior is as follows:

  • If both values are zeros, regardless of the sign of either zero, the result is the second value.
  • If either value is a NaN, regardless of the value of FPCR.DN, the result is the second value.

    • This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

    Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

    Encoding: Floating-point

    313029282726252423222120191817161514131211109876543210
    000111101010010
    MSftypeRmopRnRd

    Half-precision (ftype == 11)

    FMAX <Hd>, <Hn>, <Hm>

    Single-precision (ftype == 00)

    FMAX <Sd>, <Sn>, <Sm>

    Double-precision (ftype == 01)

    FMAX <Dd>, <Dn>, <Dm>

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF);
if ftype == '10' then EndOfDecode(Decode_UNDEF);
if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF);

constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);

constant integer esize = 8 << UInt(ftype EOR '10');

    Operation

    CheckFPEnabled64();
constant bits(esize) operand1 = V[n, esize];
constant bits(esize) operand2 = V[m, esize];

bits(128) result = if IsMerging(FPCR) then V[n, 128] else Zeros(128);

Elem[result, 0, esize] = FPMax(operand1, operand2, FPCR);

V[d, 128] = result;

    Explanations

    <Hd>: Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
    <Hn>: Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
    <Hm>: Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
    <Sd>: Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
    <Sn>: Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
    <Sm>: Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.
    <Dd>: Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
    <Dn>: Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.
    <Dm>: Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.