FMAX (immediate)

Floating-point maximum with immediate (predicated)

Determine the maximum of an immediate and each active floating-point element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate may take the value +0.0 or +1.0 only.

When FPCR.AH is 0, the behavior is as follows:

  • Negative zero compares less than positive zero.
  • When FPCR.DN is 0, if the element is a NaN, the result is a quiet NaN.
  • When FPCR.DN is 1, if the element is a NaN, the result is Default NaN.

    • When FPCR.AH is 1, the behavior is as follows:

  • If both the element and the immediate are zeros, regardless of the sign of either zero, the result is the immediate.
  • If the element is a NaN, regardless of the value of FPCR.DN, the result is the immediate.

    • Inactive elements in the destination vector register remain unmodified.

    Encoding: SVE

    Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

    313029282726252423222120191817161514131211109876543210
    011001010111101000000
    sizeopcPgi1Zdn

    FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
if size == '00' then EndOfDecode(Decode_UNDEF);
constant integer esize = 8 << UInt(size);
constant integer g = UInt(Pg);
constant integer dn = UInt(Zdn);
constant bits(esize) imm = if i1 == '0' then Zeros(esize) else FPOne('0', esize);

    Operation

    CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant bits(PL) mask = P[g, PL];
constant bits(VL) operand1 = Z[dn, VL];
bits(VL) result;

for e = 0 to elements-1
    constant bits(esize) element1 = Elem[operand1, e, esize];
    if ActivePredicateElement(mask, e, esize) then
        Elem[result, e, esize] = FPMax(element1, imm, FPCR);
    else
        Elem[result, e, esize] = element1;

Z[dn, VL] = result;

    Explanations

    <Zdn>: Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.
    <T>: <Pg>: Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
    <const>:

    Operational Notes

    This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE: