FMAXNMP (vector)

Floating-point maximum number pairwise (vector)

This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

Regardless of the value of FPCR.AH, the behavior is as follows for each pairwise operation:

  • Negative zero compares less than positive zero.
  • If one element is numeric and the other is a quiet NaN, the result is the numeric value.
  • When FPCR.DN is 0, if either element is a signaling NaN or if both elements are NaNs, the result is a quiet NaN.
  • When FPCR.DN is 1, if either element is a signaling NaN or if both elements are NaNs, the result is Default NaN.

    • This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

    Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

    Encoding: Half-precision

    Variants: FEAT_AdvSIMD && FEAT_FP16 (FEAT_AdvSIMD && FEAT_FP16)

    313029282726252423222120191817161514131211109876543210
    0101110010000001
    QUaRmopcodeRnRd

    FMAXNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
    EndOfDecode(Decode_UNDEF);

constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 16;
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;

    Encoding: Single-precision and double-precision

    Variants: FEAT_AdvSIMD (ARMv8.0)

    313029282726252423222120191817161514131211109876543210
    010111001110001
    QUo1szRmopcodeRnRd

    FMAXNMP <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF);
if sz:Q == '10' then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 32 << UInt(sz);
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;

    Operation

    CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand1 = V[n, datasize];
constant bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
constant bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[concat, 2*e, esize];
    element2 = Elem[concat, (2*e)+1, esize];
    Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
V[d, datasize] = result;

    Explanations

    <Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
    <T>: <T>: <Vn>: Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
    <Vm>: Is the name of the second SIMD&FP source register, encoded in the "Rm" field.