FMAXNMV

Floating-point maximum number across vector

This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

Regardless of the value of FPCR.AH, the behavior is as follows:

  • Negative zero compares less than positive zero.
  • If one value is numeric and the other is a quiet NaN, the result is the numeric value.
  • When FPCR.DN is 0, if either value is a signaling NaN or if both values are NaNs, the result is a quiet NaN.
  • When FPCR.DN is 1, if either value is a signaling NaN or if both values are NaNs, the result is Default NaN.

    • This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

    Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

    Encoding: Half-precision

    Variants: FEAT_AdvSIMD && FEAT_FP16 (FEAT_AdvSIMD && FEAT_FP16)

    313029282726252423222120191817161514131211109876543210
    000111000110000110010
    QUo1opcodeRnRd

    FMAXNMV <V><d>, <Vn>.<T>

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
    EndOfDecode(Decode_UNDEF);

constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 16;
constant integer datasize = 64 << UInt(Q);

    Encoding: Single-precision

    Variants: FEAT_AdvSIMD (ARMv8.0)

    313029282726252423222120191817161514131211109876543210
    0110111000110000110010
    QUo1szopcodeRnRd

    FMAXNMV S<d>, <Vn>.4S

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF);
if sz:Q != '01' then EndOfDecode(Decode_UNDEF);        // .4S only

constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 32;
constant integer datasize = 64 << UInt(Q);

    Operation

    CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand = V[n, datasize];
V[d, esize] = FPReduce(ReduceOp_FMAXNUM, operand, esize, FPCR);

    Explanations

    <V>: Is the destination width specifier, H.
    <d>: Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
    <Vn>: Is the name of the SIMD&FP source register, encoded in the "Rn" field.
    <T>: