FMIN (vector)

Floating-point minimum (vector)

This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

When FPCR.AH is 0, the behavior is as follows:

Negative zero compares less than positive zero.

When FPCR.DN is 0, if either element is a NaN, the result is a quiet NaN.

When FPCR.DN is 1, if either element is a NaN, the result is Default NaN.

When FPCR.AH is 1, the behavior is as follows:

If both elements are zeros, regardless of the sign of either zero, the result is the second element.

If either element is a NaN, regardless of the value of FPCR.DN, the result is the second element.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Half-precision

Variants: FEAT_AdvSIMD && FEAT_FP16 (FEAT_AdvSIMD && FEAT_FP16)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		0	0	1	1	1	0	1	1	0						0	0	1	1	0	1
	Q	U						o1			Rm							opcode				Rn					Rd

FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
    EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 16;
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;

Encoding: Single-precision and double-precision

Variants: FEAT_AdvSIMD (ARMv8.0)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		0	0	1	1	1	0	1		1						1	1	1	1	0	1
	Q	U						o1	sz		Rm					opcode						Rn					Rd

FMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF);
if sz:Q == '10' then EndOfDecode(Decode_UNDEF);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer esize = 32 << UInt(sz);
constant integer datasize = 64 << UInt(Q);
constant integer elements = datasize DIV esize;

Operation

CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand1 = V[n, datasize];
constant bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPMin(element1, element2, FPCR);
V[d, datasize] = result;

Explanations

<Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>: <T>: <Vn>: Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>: Is the name of the second SIMD&FP source register, encoded in the "Rm" field.