FMLA (multiple vectors)

Multi-vector floating-point fused multiply-add

This instruction multiplies the corresponding floating-point elements of the two or four first and second source vectors and destructively adds these values without intermediate rounding to the corresponding elements of the ZA single-vector groups.

The single-vector group within each half of or each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo half or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction follows SME ZA-targeting floating-point behaviors.

This instruction is unpredicated.

ID_AA64SMFR0_EL1.F64F64 indicates whether the double-precision variant is implemented, and ID_AA64SMFR0_EL1.F16F16 indicates whether the half-precision variant is implemented.

Encoding: Two ZA single-vectors

Variants: FEAT_SME2 (ARMv9.3)

313029282726252423222120191817161514131211109876543210
110000011100110000
szZmRvZnSoff3

FMLA ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zn1>.<T>-<Zn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> }

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF);
if sz == '1' && !IsFeatureImplemented(FEAT_SME_F64F64) then EndOfDecode(Decode_UNDEF);
constant integer v = UInt('010':Rv);
constant integer esize = 32 << UInt(sz);
constant integer n = UInt(Zn:'0');
constant integer m = UInt(Zm:'0');
constant integer offset = UInt(off3);
constant integer nreg = 2;

Encoding: Two ZA single-vectors of half-precision elements

Variants: FEAT_SME_F16F16 (ARMv9.4)

313029282726252423222120191817161514131211109876543210
1100000110100100001
szZmRvZnSoff3

FMLA ZA.H[<Wv>, <offs>{, VGx2}], { <Zn1>.H-<Zn2>.H }, { <Zm1>.H-<Zm2>.H }

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME_F16F16) then EndOfDecode(Decode_UNDEF);
constant integer v = UInt('010':Rv);
constant integer esize = 16;
constant integer n = UInt(Zn:'0');
constant integer m = UInt(Zm:'0');
constant integer offset = UInt(off3);
constant integer nreg = 2;

Encoding: Four ZA single-vectors

Variants: FEAT_SME2 (ARMv9.3)

313029282726252423222120191817161514131211109876543210
11000001110101100000
szZmRvZnSoff3

FMLA ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zn1>.<T>-<Zn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> }

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME2) then EndOfDecode(Decode_UNDEF);
if sz == '1' && !IsFeatureImplemented(FEAT_SME_F64F64) then EndOfDecode(Decode_UNDEF);
constant integer v = UInt('010':Rv);
constant integer esize = 32 << UInt(sz);
constant integer n = UInt(Zn:'00');
constant integer m = UInt(Zm:'00');
constant integer offset = UInt(off3);
constant integer nreg = 4;

Encoding: Four ZA single-vectors of half-precision elements

Variants: FEAT_SME_F16F16 (ARMv9.4)

313029282726252423222120191817161514131211109876543210
110000011010101000001
szZmRvZnSoff3

FMLA ZA.H[<Wv>, <offs>{, VGx4}], { <Zn1>.H-<Zn4>.H }, { <Zm1>.H-<Zm4>.H }

Decoding algorithm

if !IsFeatureImplemented(FEAT_SME_F16F16) then EndOfDecode(Decode_UNDEF);
constant integer v = UInt('010':Rv);
constant integer esize = 16;
constant integer n = UInt(Zn:'00');
constant integer m = UInt(Zm:'00');
constant integer offset = UInt(off3);
constant integer nreg = 4;

Operation

CheckStreamingSVEAndZAEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant integer vectors = VL DIV 8;
constant integer vstride = vectors DIV nreg;
constant bits(32) vbase = X[v, 32];
integer vec = (UInt(vbase) + offset) MOD vstride;
bits(VL) result;

for r = 0 to nreg-1
    constant bits(VL) op1 = Z[n+r, VL];
    constant bits(VL) op2 = Z[m+r, VL];
    constant bits(VL) op3 = ZAvector[vec, VL];
    for e = 0 to elements-1
        constant bits(esize) elem1 = Elem[op1, e, esize];
        constant bits(esize) elem2 = Elem[op2, e, esize];
        constant bits(esize) elem3 = Elem[op3, e, esize];
        Elem[result, e, esize] = FPMulAdd_ZA(elem3, elem1, elem2, FPCR);
    ZAvector[vec, VL] = result;
    vec = vec + vstride;

Explanations

<T>: <Wv>: Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.
<offs>: Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.
<Zn1>: For the "Two ZA single-vectors of half-precision elements" and "Two ZA single-vectors" variants: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.
<Zn1>: For the "Four ZA single-vectors of half-precision elements" and "Four ZA single-vectors" variants: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.
<Zn2>: Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.
<Zm1>: For the "Two ZA single-vectors of half-precision elements" and "Two ZA single-vectors" variants: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 2.
<Zm1>: For the "Four ZA single-vectors of half-precision elements" and "Four ZA single-vectors" variants: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 4.
<Zm2>: Is the name of the second scalable vector register of the second source multi-vector group, encoded as "Zm" times 2 plus 1.
<Zn4>: Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.
<Zm4>: Is the name of the fourth scalable vector register of the second source multi-vector group, encoded as "Zm" times 4 plus 3.