FMMLA (widening, 8-bit floating-point to single-precision)

8-bit floating-point matrix multiply-accumulate to single-precision

This instruction performs the fused sum-of-products within each eight adjacent 8-bit elements while multiplying the 2×8 matrix of 8-bit floating-point values in the first source vector by the 8×2 matrix of 8-bit floating-point values in the second source vector. The single-precision sum-of-products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the 2x2 single-precision matrix in the destination vector. This is equivalent to accumulating 8-way dot product per destination element.

The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.

Encoding: Advanced SIMD

Variants: FEAT_F8F32MM (ARMv9.6)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	1	1	1	0	1	0	0						1	1	1	0	1	1
	Q	U						size			Rm						opcode					Rn					Rd

FMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B

Decoding algorithm

if !IsFeatureImplemented(FEAT_F8F32MM) then EndOfDecode(Decode_UNDEF);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer d = UInt(Rd);

Operation

CheckFPMREnabled();
CheckFPAdvSIMDEnabled64();
constant bits(128) op1 = V[n, 128];
constant bits(128) op2 = V[m, 128];
constant bits(128) acc = V[d, 128];

V[d, 128] = FP8MatMulAddFP(acc, op1, op2, 8, FPCR, FPMR);

Explanations

<Vd>: Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field.
<Vn>: Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>: Is the name of the second SIMD&FP source register, encoded in the "Rm" field.