FMOV (vector, immediate)

Floating-point move immediate (vector)

This instruction copies an immediate floating-point constant into every element of the SIMD&FP destination register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Half-precision

Variants: FEAT_AdvSIMD && FEAT_FP16 (FEAT_AdvSIMD && FEAT_FP16)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		0	0	1	1	1	1	0	0	0	0	0				1	1	1	1	1	1
	Q	op											a	b	c	cmode				o2		d	e	f	g	h	Rd

FMOV <Vd>.<T>, #<imm>, see x[Modified immediate constants in A64 floating-point instructions](CJAFAFAI)." class="text-blue-400 hover:text-yellow-300"><imm>

Decoding algorithm

if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
    EndOfDecode(Decode_UNDEF);

constant integer rd = UInt(Rd);

constant integer datasize = 64 << UInt(Q);
constant bits(8) imm8 = a:b:c:d:e:f:g:h;
constant bits(16) imm16 = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>, 2):imm8<5:0>:Zeros(6);
constant bits(datasize) imm = Replicate(imm16, datasize DIV 16);

Encoding: Single-precision and double-precision

Variants: FEAT_AdvSIMD (ARMv8.0)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0			0	1	1	1	1	0	0	0	0	0				1	1	1	1	0	1
	Q	op											a	b	c	cmode				o2		d	e	f	g	h	Rd

Single-precision (op == 0)

FMOV <Vd>.<T>, #<imm>, see x[Modified immediate constants in A64 floating-point instructions](CJAFAFAI)." class="text-blue-400 hover:text-yellow-300"><imm>

Double-precision (Q == 1 && op == 1)

FMOV <Vd>.2D, #<imm>, see x[Modified immediate constants in A64 floating-point instructions](CJAFAFAI)." class="text-blue-400 hover:text-yellow-300"><imm>

Decoding algorithm

if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF);
if cmode:op == '11111' then
    // FMOV Dn,#imm is in main FP instruction set
    if Q == '0' then EndOfDecode(Decode_UNDEF);

constant integer rd = UInt(Rd);
constant integer datasize = 64 << UInt(Q);
constant bits(64) imm64 = AdvSIMDExpandImm(op, cmode, a:b:c:d:e:f:g:h);
constant bits(datasize) imm = Replicate(imm64, datasize DIV 64);

Operation

CheckFPAdvSIMDEnabled64();
V[rd, datasize] = imm;

Explanations

<Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>: <T>: <imm>: Is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h". For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in A64 floating-point instructions.