FMOV (scalar, immediate)

Floating-point move immediate (scalar)

This instruction copies a floating-point immediate constant into the SIMD&FP destination register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Floating point constant in 8 bits

313029282726252423222120191817161514131211109876543210
00011110110000000
MSftypeimm8imm5Rd

Half-precision (ftype == 11)

FMOV <Hd>, #<imm>, see x[Modified immediate constants in A64 floating-point instructions](CJAFAFAI)." class="text-blue-400 hover:text-yellow-300"><imm>

Single-precision (ftype == 00)

FMOV <Sd>, #<imm>, see x[Modified immediate constants in A64 floating-point instructions](CJAFAFAI)." class="text-blue-400 hover:text-yellow-300"><imm>

Double-precision (ftype == 01)

FMOV <Dd>, #<imm>, see x[Modified immediate constants in A64 floating-point instructions](CJAFAFAI)." class="text-blue-400 hover:text-yellow-300"><imm>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF);
if ftype == '10' then EndOfDecode(Decode_UNDEF);
if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF);

constant integer d = UInt(Rd);

constant integer datasize = 8 << UInt(ftype EOR '10');
constant bits(datasize) imm = VFPExpandImm(imm8, datasize);

Operation

CheckFPEnabled64();

V[d, datasize] = imm;

Explanations

<Hd>: Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<imm>: Is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in the "imm8" field. For details of the range of constants available and the encoding of <imm>, see Modified immediate constants in A64 floating-point instructions.
<Sd>: Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Dd>: Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.