FRINT32Z (scalar)

Floating-point round to 32-bit integer toward zero (scalar)

This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 32-bit integer size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

A zero input returns a zero result with the same sign. When the result value is not numerically equal to the {corresponding} input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Floating-point

Variants: FEAT_FRINTTS (ARMv8.5)

313029282726252423222120191817161514131211109876543210
000111100x101000010000
MSftypeopRnRd

Single-precision (ftype == 00)

FRINT32Z <Sd>, <Sn>

Double-precision (ftype == 01)

FRINT32Z <Dd>, <Dn>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FRINTTS) then EndOfDecode(Decode_UNDEF);
if ftype IN {'1x'} then EndOfDecode(Decode_UNDEF);

constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer esize = 32 << UInt(ftype<0>);
constant integer intsize = 32;

constant FPRounding rounding = FPRounding_ZERO;

Operation

CheckFPEnabled64();

constant bits(esize) operand = V[n, esize];
bits(128) result = if IsMerging(FPCR) then V[d, 128] else Zeros(128);

Elem[result, 0, esize] = FPRoundIntN(operand, FPCR, rounding, intsize);

V[d, 128] = result;

Explanations

<Sd>: Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Sn>: Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<Dd>: Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Dn>: Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.