FSCALE

Floating-point adjust exponent by vector

This instruction multiplies the floating-point elements of the first source vector by 2.0 to the power of the signed integer values in the corresponding elements of the second source vector, and places the results in the corresponding elements of the destination vector.

Encoding: Half-precision

Variants: FEAT_FP8 (ARMv9.5)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		1	0	1	1	1	0	1	1	0						0	0	1	1	1	1
	Q	U						a			Rm							opcode				Rn					Rd

FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF);
constant integer esize = 16;
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer datasize = if Q == '1' then 128 else 64;
constant integer elements = datasize DIV esize;

Encoding: Single-precision and double-precision

Variants: FEAT_FP8 (ARMv9.5)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		1	0	1	1	1	0	1	x	1						1	1	1	1	1	1
	Q	U						size			Rm					opcode						Rn					Rd

FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP8) then EndOfDecode(Decode_UNDEF);
if Q == '0' && size == '11' then EndOfDecode(Decode_UNDEF);
constant integer esize = 8 << UInt(size);
constant integer d = UInt(Rd);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer datasize = if Q == '1' then 128 else 64;
constant integer elements = datasize DIV esize;

Operation

CheckFPAdvSIMDEnabled64();
constant bits(datasize) operand1 = V[n, datasize];
constant bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;

for e = 0 to elements-1
    constant bits(esize) op1 = Elem[operand1, e, esize];
    constant integer op2     = SInt(Elem[operand2, e, esize]);
    Elem[result, e, esize] = FPScale(op1, op2, FPCR);

V[d, datasize] = result;

Explanations

<Vd>: Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>: <T>: <Vn>: Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>: Is the name of the second SIMD&FP source register, encoded in the "Rm" field.