INSR (SIMD&FP scalar)

Insert SIMD&FP scalar register in shifted vector

Shift the destination vector left by one element, and then place a copy of the SIMD&FP scalar register in element 0 of the destination vector. This instruction is unpredicated.

Encoding: SVE

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1			1	1	0	1	0	0	0	0	1	1	1	0
								size														Vm					Zdn

INSR <Zdn>.<T>, <V><m>

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer esize = 8 << UInt(size);
constant integer dn = UInt(Zdn);
constant integer m = UInt(Vm);

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant bits(VL) dest = Z[dn, VL];
constant bits(esize) src = V[m, esize];
Z[dn, VL] = dest<(VL-esize)-1:0> : src;

Explanations

<Zdn>: Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.
<T>: <V>: <m>: Is the number [0-31] of the source SIMD&FP register, encoded in the "Vm" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its registers.
  • The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:

• The MOVPRFX must be unpredicated.
• The MOVPRFX must specify the same destination register as this instruction.
• The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.