LD1D (scalar plus immediate, single register)

Contiguous load unsigned doublewords to vector (immediate index)

Contiguous load of unsigned doublewords to elements of a vector register from the memory address generated by a 64-bit scalar base and immediate index in the range -8 to 7 which is multiplied by the vector's in-memory size, irrespective of predication, and added to the base address. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.

The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Encoding: 64-bit element

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

313029282726252423222120191817161514131211109876543210
101001011110101
dtypeimm4PgRnZt

LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 64;
constant boolean unsigned = TRUE;
constant integer offset = SInt(imm4);

Encoding: 128-bit element

Variants: FEAT_SVE2p1 (ARMv9.4)

313029282726252423222120191817161514131211109876543210
101001011001001
dtypeimm4PgRnZt

LD1D { <Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE2p1) then EndOfDecode(Decode_UNDEF);
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer g = UInt(Pg);
constant integer esize = 128;
constant integer msize = 64;
constant boolean unsigned = TRUE;
constant integer offset = SInt(imm4);

Operation

if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
constant bits(PL) mask = P[g, PL];
bits(64) addr;
bits(VL) result;
bits(msize) data;
constant integer mbytes = msize DIV 8;
constant boolean contiguous = TRUE;
constant boolean nontemporal = FALSE;
constant boolean tagchecked = n != 31;
constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous,
                                                     tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();

base = if n == 31 then SP[64] else X[n, 64];
addr = AddressAdd(base, offset * elements * mbytes, accdesc);

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        data = Mem[addr, mbytes, accdesc];
        Elem[result, e, esize] = Extend(data, esize, unsigned);
    else
        Elem[result, e, esize] = Zeros(esize);
    addr = AddressIncrement(addr, mbytes, accdesc);

Z[t, VL] = result;

Explanations

<Zt>: Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.
<Pg>: Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<imm>: Is the optional signed immediate vector offset, in the range -8 to 7, defaulting to 0, encoded in the "imm4" field.

Operational Notes

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.