LD1D (scalar plus vector)

Gather load doublewords to vector (vector index)

Gather load of doublewords to active elements of a vector register from memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 8. Inactive elements will not cause a read from Device memory or signal faults, and are set to zero in the destination vector.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

Encoding: 32-bit unpacked scaled offset

Variants: FEAT_SVE (PROFILE_A)

313029282726252423222120191817161514131211109876543210
1100010111010
opcxsZmUffPgRnZt

LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF);
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 64;
constant integer offs_size = 32;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = xs == '0';
constant integer scale = 3;

Encoding: 32-bit unpacked unscaled offset

Variants: FEAT_SVE (PROFILE_A)

313029282726252423222120191817161514131211109876543210
1100010110010
mszxsZmUffPgRnZt

LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF);
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 64;
constant integer offs_size = 32;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = xs == '0';
constant integer scale = 0;

Encoding: 64-bit scaled offset

Variants: FEAT_SVE (PROFILE_A)

313029282726252423222120191817161514131211109876543210
11000101111110
opcZmUffPgRnZt

LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF);
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 64;
constant integer offs_size = 64;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = TRUE;
constant integer scale = 3;

Encoding: 64-bit unscaled offset

Variants: FEAT_SVE (PROFILE_A)

313029282726252423222120191817161514131211109876543210
11000101110110
mszZmUffPgRnZt

LD1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) then EndOfDecode(Decode_UNDEF);
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Zm);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 64;
constant integer offs_size = 64;
constant boolean unsigned = TRUE;
constant boolean offs_unsigned = TRUE;
constant integer scale = 0;

Operation

CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
constant bits(PL) mask = P[g, PL];
bits(VL) offset;
bits(VL) result;
bits(msize) data;
constant integer mbytes = msize DIV 8;
constant boolean contiguous = FALSE;
constant boolean nontemporal = FALSE;
constant boolean tagchecked = TRUE;
constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous,
                                                     tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();
    base = if n == 31 then SP[64] else X[n, 64];
    offset = Z[m, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        constant integer off = Int(Elem[offset, e, esize], offs_unsigned);
        constant bits(64) addr = AddressAdd(base, off << scale, accdesc);
        data = Mem[addr, mbytes, accdesc];
        Elem[result, e, esize] = Extend(data, esize, unsigned);
    else
        Elem[result, e, esize] = Zeros(esize);

Z[t, VL] = result;

Explanations

<Zt>: Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.
<Pg>: Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Zm>: Is the name of the offset scalable vector register, encoded in the "Zm" field.
<mod>:

Operational Notes

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.