LD1SH (scalar plus scalar)

Contiguous load signed halfwords to vector (scalar index)

Contiguous load of signed halfwords to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 2 and added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.

Encoding: 32-bit element

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	0	0	1	0	1	0	0	1	!= 11111					0	1	0
							dtype				Rm								Pg			Rn					Zt

LD1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
if Rm == '11111' then EndOfDecode(Decode_UNDEF);
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer g = UInt(Pg);
constant integer esize = 32;
constant integer msize = 16;
constant boolean unsigned = FALSE;

Encoding: 64-bit element

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	0	0	1	0	1	0	0	0	!= 11111					0	1	0
							dtype				Rm								Pg			Rn					Zt

LD1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
if Rm == '11111' then EndOfDecode(Decode_UNDEF);
constant integer t = UInt(Zt);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer g = UInt(Pg);
constant integer esize = 64;
constant integer msize = 16;
constant boolean unsigned = FALSE;

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(64) base;
constant bits(PL) mask = P[g, PL];
bits(VL) result;
bits(msize) data;
bits(64) offset;
bits(64) addr;
constant integer mbytes = msize DIV 8;
constant boolean contiguous = TRUE;
constant boolean nontemporal = FALSE;
constant boolean tagchecked = TRUE;
constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous,
                                                     tagchecked);

if !AnyActiveElement(mask, esize) then
    if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then
        CheckSPAlignment();
else
    if n == 31 then CheckSPAlignment();

base = if n == 31 then SP[64] else X[n, 64];
offset = X[m, 64];
addr = AddressAdd(base, UInt(offset) * mbytes, accdesc);

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        data = Mem[addr, mbytes, accdesc];
        Elem[result, e, esize] = Extend(data, esize, unsigned);
    else
        Elem[result, e, esize] = Zeros(esize);
    addr = AddressIncrement(addr, mbytes, accdesc);

Z[t, VL] = result;

Explanations

<Zt>: Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.
<Pg>: Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xm>: Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.

Operational Notes

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.