LDAPUR (SIMD&FP)

Load-acquire RCpc SIMD&FP register (unscaled offset)

This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an optional immediate offset.

The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:

There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release, created by having a Store-Release followed by a Load-AcquirePC instruction.

The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer does not make the write of the Store-Release globally observed.

This difference in memory ordering is not described in the pseudocode.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Encoding: Unscaled offset

Variants: FEAT_FP && FEAT_LRCPC3 (FEAT_FP && FEAT_LRCPC3)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		0	1	1	1	0	1	x	1	0										1	0
size								opc			imm9											Rn					Rt

8-bit (size == 00 && opc == 01)

LDAPUR <Bt>, [<Xn|SP>{, #<simm>}]

16-bit (size == 01 && opc == 01)

LDAPUR <Ht>, [<Xn|SP>{, #<simm>}]

32-bit (size == 10 && opc == 01)

LDAPUR <St>, [<Xn|SP>{, #<simm>}]

64-bit (size == 11 && opc == 01)

LDAPUR <Dt>, [<Xn|SP>{, #<simm>}]

128-bit (size == 00 && opc == 11)

LDAPUR <Qt>, [<Xn|SP>{, #<simm>}]

Decoding algorithm

if !IsFeatureImplemented(FEAT_FP) || !IsFeatureImplemented(FEAT_LRCPC3) then
    EndOfDecode(Decode_UNDEF);
if opc<1> == '1' && size != '00' then EndOfDecode(Decode_UNDEF);
constant integer scale = if opc<1> == '1' then 4 else UInt(size);
constant bits(64) offset = SignExtend(imm9, 64);

Operation

constant integer t = UInt(Rt);
constant integer n = UInt(Rn);
constant integer datasize = 8 << scale;
constant boolean nontemporal = FALSE;
constant boolean tagchecked = n != 31;

CheckFPAdvSIMDEnabled64();
bits(64) address;

constant AccessDescriptor accdesc = CreateAccDescASIMDAcqRel(MemOp_LOAD, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[64];
else
    address = X[n, 64];

address = AddressAdd(address, offset, accdesc);

V[t, datasize] = Mem[address, datasize DIV 8, accdesc];

Explanations

<Bt>: Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<simm>: Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.
<Ht>: Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
<St>: Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
<Dt>: Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.
<Qt>: Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

Operational Notes

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.