LDAPURH

Load-acquire RCpc register halfword (unscaled)

This instruction calculates an address from a base register and an immediate offset, loads a halfword from memory, zero-extends it, and writes it to a register.

The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:

  • There is no ordering requirement, separate from the requirements of a Load-AcquirePC or a Store-Release, created by having a Store-Release followed by a Load-AcquirePC instruction.
  • The reading of a value written by a Store-Release by a Load-AcquirePC instruction by the same observer does not make the write of the Store-Release globally observed.

    • This difference in memory ordering is not described in the pseudocode.

    For information about addressing modes, see Load/Store addressing modes.

    Encoding: Unscaled offset

    Variants: FEAT_LRCPC2 (ARMv8.4)

    313029282726252423222120191817161514131211109876543210
    0101100101000
    sizeopcimm9RnRt

    LDAPURH <Wt>, [<Xn|SP>{, #<simm>}]

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_LRCPC2) then EndOfDecode(Decode_UNDEF);
constant bits(64) offset = SignExtend(imm9, 64);

    Operation

    constant integer t = UInt(Rt);
constant integer n = UInt(Rn);
constant integer datasize = 16;
constant boolean tagchecked = n != 31;
    bits(64) address;

constant AccessDescriptor accdesc = CreateAccDescLDAcqPC(tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[64];
else
    address = X[n, 64];

address = AddressAdd(address, offset, accdesc);

constant bits(datasize) data = Mem[address, datasize DIV 8, accdesc];
X[t, 32] = ZeroExtend(data, 32);

    Explanations

    <Wt>: Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
    <Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
    <simm>: Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

    Operational Notes

    If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.