LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH

Atomic bit clear on halfword in memory

This instruction atomically loads a 16-bit halfword from memory, performs a bitwise AND with the complement of the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

  • If the destination register is not WZR, LDCLRAH and LDCLRALH load from memory with acquire semantics.
  • LDCLRLH and LDCLRALH store to memory with release semantics.
  • LDCLRH has neither acquire nor release semantics.

    • For more information about memory ordering semantics, see Load-Acquire, Store-Release.

    For information about addressing modes, see Load/Store addressing modes.

    Encoding: Integer

    Variants: FEAT_LSE (ARMv8.1)

    313029282726252423222120191817161514131211109876543210
    011110001000100
    sizeVRARRso3opcRnRt

    No memory ordering (A == 0 && R == 0)

    LDCLRH <Ws>, <Wt>, [<Xn|SP>]

    Acquire (A == 1 && R == 0)

    LDCLRAH <Ws>, <Wt>, [<Xn|SP>]

    Acquire-release (A == 1 && R == 1)

    LDCLRALH <Ws>, <Wt>, [<Xn|SP>]

    Release (A == 0 && R == 1)

    LDCLRLH <Ws>, <Wt>, [<Xn|SP>]

    Decoding algorithm

    if !IsFeatureImplemented(FEAT_LSE) then EndOfDecode(Decode_UNDEF);
constant integer s = UInt(Rs);
constant integer t = UInt(Rt);
constant integer n = UInt(Rn);

constant boolean acquire = A == '1' && Rt != '11111';
constant boolean release = R == '1';
constant boolean tagchecked = n != 31;

    Operation

    bits(64) address;

constant boolean privileged = PSTATE.EL != EL0;
constant AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_BIC, acquire, release,
                                                          tagchecked, privileged);

if n == 31 then
    CheckSPAlignment();
    address = SP[64];
else
    address = X[n, 64];

constant bits(16) comparevalue = bits(16) UNKNOWN; // Irrelevant when not executing CAS
constant bits(16) value = X[s, 16];
constant bits(16) data = MemAtomic(address, comparevalue, value, accdesc);

if t != 31 then
    X[t, 32] = ZeroExtend(data, 32);

    Explanations

    <Ws>: Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
    <Wt>: Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
    <Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

    Operational Notes

    If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.