LDFMAX, LDFMAXA, LDFMAXAL, LDFMAXL

Floating-point atomic maximum in memory

This instruction atomically loads a 16-bit, 32-bit, or 64-bit value from memory, computes the floating-point maximum with the value held in a register, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

LDFMAXA and LDFMAXAL load from memory with acquire semantics.

LDFMAXL and LDFMAXAL store to memory with release semantics.

LDFMAX has neither acquire nor release semantics.

This instruction:

Disables alternative floating-point behaviors, as if FPCR.AH is 0.

Generates only the default NaN, as if FPCR.DN is 1.

Does not modify the cumulative FPSR exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).

Disables trapped floating-point exceptions, as if the FPCR trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

Encoding: Floating-point

Variants: FEAT_LSFE (ARMv9.6)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		1	1	1	1	0	0			1						0	1	0	0	0	0
size					VR			A	R		Rs					o3	opc					Rn					Rt

Half-precision no memory ordering (size == 01 && A == 0 && R == 0)

LDFMAX <Hs>, <Ht>, [<Xn|SP>]

Half-precision acquire (size == 01 && A == 1 && R == 0)

LDFMAXA <Hs>, <Ht>, [<Xn|SP>]

Half-precision acquire-release (size == 01 && A == 1 && R == 1)

LDFMAXAL <Hs>, <Ht>, [<Xn|SP>]

Half-precision release (size == 01 && A == 0 && R == 1)

LDFMAXL <Hs>, <Ht>, [<Xn|SP>]

Single-precision no memory ordering (size == 10 && A == 0 && R == 0)

LDFMAX <Ss>, <St>, [<Xn|SP>]

Single-precision acquire (size == 10 && A == 1 && R == 0)

LDFMAXA <Ss>, <St>, [<Xn|SP>]

Single-precision acquire-release (size == 10 && A == 1 && R == 1)

LDFMAXAL <Ss>, <St>, [<Xn|SP>]

Single-precision release (size == 10 && A == 0 && R == 1)

LDFMAXL <Ss>, <St>, [<Xn|SP>]

Double-precision no memory ordering (size == 11 && A == 0 && R == 0)

LDFMAX <Ds>, <Dt>, [<Xn|SP>]

Double-precision acquire (size == 11 && A == 1 && R == 0)

LDFMAXA <Ds>, <Dt>, [<Xn|SP>]

Double-precision acquire-release (size == 11 && A == 1 && R == 1)

LDFMAXAL <Ds>, <Dt>, [<Xn|SP>]

Double-precision release (size == 11 && A == 0 && R == 1)

LDFMAXL <Ds>, <Dt>, [<Xn|SP>]

Decoding algorithm

if !IsFeatureImplemented(FEAT_LSFE) then EndOfDecode(Decode_UNDEF);

constant integer t = UInt(Rt);
constant integer n = UInt(Rn);
constant integer s = UInt(Rs);

constant integer datasize = 8 << UInt(size);
constant boolean acquire = A == '1';
constant boolean release = R == '1';
constant boolean tagchecked = n != 31;

Operation

CheckFPEnabled64();
bits(64) address;
bits(datasize) value;
bits(datasize) data;
constant AccessDescriptor accdesc = CreateAccDescFPAtomicOp(MemAtomicOp_FPMAX, acquire,
                                                            release, tagchecked);

value = V[s, datasize];
if n == 31 then
    CheckSPAlignment();
    address = SP[64];
else
    address = X[n, 64];

constant bits(datasize) comparevalue = bits(datasize) UNKNOWN; // Irrelevant when not executing CAS
data = MemAtomic(address, comparevalue, value, accdesc);

V[t, datasize] = data;

Explanations

<Hs>: Is the 16-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
<Ht>: Is the 16-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Ss>: Is the 32-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
<St>: Is the 32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.
<Ds>: Is the 64-bit name of the SIMD&FP register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
<Dt>: Is the 64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.