LDTADD, LDTADDA, LDTADDAL, LDTADDL

Atomic add unprivileged

This instruction atomically loads a 32-bit word or 64-bit doubleword from memory, adds the value held in a register to it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

If the destination register is not one of WZR, or XZR, LDTADDA and LDTADDAL load from memory with acquire semantics.

LDTADDL and LDTADDAL store to memory with release semantics.

LDTADD has neither acquire nor release semantics.

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

Explicit Memory effects produced by the instruction behave as if the instruction was executed at EL0 if the Effective value of PSTATE.UAO is 0 and either:

The instruction is executed at EL1.

The instruction is executed at EL2 when the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}.

Otherwise, the Explicit Memory effects operate with the restrictions determined by the Exception level at which the instruction is executed.

Encoding: Integer

Variants: FEAT_LSUI (ARMv9.6)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		0	1	1	0	0	1			1						0	0	0	0	0	1
	sz							A	R		Rs					o3	opc					Rn					Rt

32-bit no memory ordering (sz == 0 && A == 0 && R == 0)

LDTADD <Ws>, <Wt>, [<Xn|SP>]

32-bit acquire (sz == 0 && A == 1 && R == 0)

LDTADDA <Ws>, <Wt>, [<Xn|SP>]

32-bit acquire-release (sz == 0 && A == 1 && R == 1)

LDTADDAL <Ws>, <Wt>, [<Xn|SP>]

32-bit release (sz == 0 && A == 0 && R == 1)

LDTADDL <Ws>, <Wt>, [<Xn|SP>]

64-bit no memory ordering (sz == 1 && A == 0 && R == 0)

LDTADD <Xs>, <Xt>, [<Xn|SP>]

64-bit acquire (sz == 1 && A == 1 && R == 0)

LDTADDA <Xs>, <Xt>, [<Xn|SP>]

64-bit acquire-release (sz == 1 && A == 1 && R == 1)

LDTADDAL <Xs>, <Xt>, [<Xn|SP>]

64-bit release (sz == 1 && A == 0 && R == 1)

LDTADDL <Xs>, <Xt>, [<Xn|SP>]

Decoding algorithm

if !IsFeatureImplemented(FEAT_LSUI) then EndOfDecode(Decode_UNDEF);
constant integer s = UInt(Rs);
constant integer t = UInt(Rt);
constant integer n = UInt(Rn);

constant integer datasize = 32 << UInt(sz);
constant integer regsize = if datasize == 64 then 64 else 32;

constant boolean acquire = A == '1' && Rt != '11111';
constant boolean release = R == '1';
constant boolean tagchecked = n != 31;

Operation

bits(64) address;

constant boolean privileged = AArch64.IsUnprivAccessPriv();
constant AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_ADD, acquire, release,
                                                          tagchecked, privileged);

if n == 31 then
    CheckSPAlignment();
    address = SP[64];
else
    address = X[n, 64];

constant bits(datasize) comparevalue = bits(datasize) UNKNOWN; // Irrelevant when not executing CAS
constant bits(datasize) value = X[s, datasize];
constant bits(datasize) data = MemAtomic(address, comparevalue, value, accdesc);

if t != 31 then
    X[t, regsize] = ZeroExtend(data, regsize);

Explanations

<Ws>: Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
<Wt>: Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xs>: Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.
<Xt>: Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

Operational Notes

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.