MOV (scalar, predicated)

Move general-purpose register to vector elements (predicated)

Move the general-purpose scalar source register to each active element in the destination vector. Inactive elements in the destination vector register remain unmodified.

Encoding: SVE

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	1	0	1			1	0	1	0	0	0	1	0	1
								size											Pg			Rn					Zd

MOV <Zd>.<T>, <Pg>/M, <R><n|SP>

Equivalent to: CPY <Zd>.<T>, <Pg>/M, <R><n|SP>

Explanations

<Zd>: Is the name of the destination scalable vector register, encoded in the "Zd" field.
<T>: <Pg>: Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<R>: <n|SP>: Is the number [0-30] of the general-purpose source register or the name SP (31), encoded in the "Rn" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
  • The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is CONSTRAINED UNPREDICTABLE:

• The MOVPRFX can be predicated or unpredicated.
• A predicated MOVPRFX must use the same governing predicate register as this instruction.
• A predicated MOVPRFX must use the larger of the destination element size and first source element size in the preferred disassembly of this instruction.
• The MOVPRFX must specify the same destination register as this instruction.
• The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.