MSRR

Move two adjacent general-purpose registers to System register

This instruction allows the PE to write an AArch64 128-bit System register from two adjacent 64-bit general-purpose registers.

Encoding: System

Variants: FEAT_SYSREG128 (ARMv9.4)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	0	1	0	1	0	1	0	1	0	1
										L		o0	op1			CRn				CRm				op2			Rt

MSRR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>, <Xt+1>

Decoding algorithm

if !IsFeatureImplemented(FEAT_SYSREG128) then EndOfDecode(Decode_UNDEF);
if Rt<0> == '1' then EndOfDecode(Decode_UNDEF);

constant integer t       = UInt(Rt);
constant integer t2      = UInt(Rt+1);
constant bits(1) sys_L   = L;
constant bits(2) sys_op0 = '1' : o0;
constant bits(3) sys_op1 = op1;
constant bits(3) sys_op2 = op2;
constant bits(4) sys_crn = CRn;
constant bits(4) sys_crm = CRm;

Operation

AArch64.CheckSystemAccess(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t, sys_L);
AArch64.SysRegWrite128(sys_op0, sys_op1, sys_crn, sys_crm, sys_op2, t, t2);

Explanations

<systemreg>: Is a System register name, encoded in "o0:op1:CRn:CRm:op2".
<op0>: <op1>: Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.
<Cn>: Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.
<Cm>: Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.
<op2>: Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.
<Xt>: Is the 64-bit name of the first general-purpose source register, encoded in the "Rt" field.
<Xt+1>: Is the 64-bit name of the second general-purpose source register, encoded as "Rt" +1.