NOTS

Bitwise invert predicate, setting the condition flags

Bitwise invert each active element of the source predicate, and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.

Encoding: Setting the condition flags

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	1	0	0	1	0	1	0	1	0	0					0	1					1					0
								op	S			Pm						Pg				o2	Pn				o3	Pd

NOTS <Pd>.B, <Pg>/Z, <Pn>.B

Equivalent to: EORS <Pd>.B, <Pg>/Z, <Pn>.B, <Pg>.B

Explanations

<Pd>: Is the name of the destination scalable predicate register, encoded in the "Pd" field.
<Pg>: Is the name of the governing scalable predicate register, encoded in the "Pg" field.
<Pn>: Is the name of the source scalable predicate register, encoded in the "Pn" field.

Operational Notes

If PSTATE.DIT is 1:

• The execution time of this instruction is independent of:
  • The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
  • The values of the NZCV flags.
• The response of this instruction to asynchronous exceptions does not vary based on:
  • The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
  • The values of the NZCV flags.

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed.