Multi-vector polynomial multiply long
Polynomial multiply over [0, 1] the corresponding even-numbered elements of the first and second source vectors, and place the results in the overlapping double-width elements of the first destination vector. Perform the same operation with odd-numbered elements of the source vectors, writing to the second destination vector. This instruction is unpredicated.
This instruction is legal when executed in Streaming SVE mode if both FEAT_SSVE_AES and FEAT_SVE_AES2 are implemented.
Variants: FEAT_SVE_AES2 (ARMv9.6)
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | ||||||||||||||
| size | Zm | Zn | Zd | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PMULL { <Zd1>.Q-<Zd2>.Q }, <Zn>.D, <Zm>.D
if !IsFeatureImplemented(FEAT_SVE_AES2) then EndOfDecode(Decode_UNDEF); constant integer esize = 128; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd:'0');
if IsFeatureImplemented(FEAT_SSVE_AES) then
CheckSVEEnabled();
else
CheckNonStreamingSVEEnabled();
constant integer VL = CurrentVL;
constant integer elements = VL DIV esize;
constant bits(VL) operand1 = Z[n, VL];
constant bits(VL) operand2 = Z[m, VL];
bits(VL) result_lo;
bits(VL) result_hi;
for e = 0 to elements-1
constant bits(esize DIV 2) element1_lo = Elem[operand1, 2*e + 0, esize DIV 2];
constant bits(esize DIV 2) element2_lo = Elem[operand2, 2*e + 0, esize DIV 2];
constant bits(esize DIV 2) element1_hi = Elem[operand1, 2*e + 1, esize DIV 2];
constant bits(esize DIV 2) element2_hi = Elem[operand2, 2*e + 1, esize DIV 2];
Elem[result_lo, e, esize] = PolynomialMult(element1_lo, element2_lo);
Elem[result_hi, e, esize] = PolynomialMult(element1_hi, element2_hi);
Z[d + 0, VL] = result_lo;
Z[d + 1, VL] = result_hi;