PRFH (scalar plus scalar)

Contiguous prefetch halfwords (scalar index)

Contiguous prefetch of halfword elements from the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 2 and added to the base address. After each element prefetch the index value is incremented, but the index register is not updated.

Arm strongly recommends the following for this instruction:

• A PE does not perform a prefetch as a result of Inactive elements.
• Software uses the predicate operand to suppress prefetches from unwanted addresses.

Encoding: SVE

Variants: FEAT_SVE || FEAT_SME (FEAT_SVE || FEAT_SME)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	0	0	0	1	0	0	1	0	0	!= 11111					1	1	0									0
							msz				Rm								Pg			Rn						prfop

PRFH <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1]

Decoding algorithm

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then
    EndOfDecode(Decode_UNDEF);
if Rm == '11111' then EndOfDecode(Decode_UNDEF);
constant integer esize = 16;
constant integer g = UInt(Pg);
constant integer n = UInt(Rn);
constant integer m = UInt(Rm);
constant integer level = UInt(prfop<2:1>);
constant boolean stream = (prfop<0> == '1');
constant PrefetchHint pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE;
constant integer scale = 1;

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
constant bits(PL) mask = P[g, PL];
bits(64) base;
bits(64) offset;

if AnyActiveElement(mask, esize) then
    base = if n == 31 then SP[64] else X[n, 64];
    offset = X[m, 64];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        constant integer eoff = UInt(offset) + e;
        constant bits(64) addr = base + (eoff << scale);
        Hint_Prefetch(addr, pref_hint, level, stream);

Explanations

<prfop>: <Pg>: Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xm>: Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.