PRFM (immediate)

Prefetch memory (immediate)

This instruction signals the memory system that data memory accesses from a specified address are likely to occur in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as making the cache line containing the specified address available at the level of cache specified by the instruction.

The effect of a PRFM instruction is IMPLEMENTATION DEFINED. For more information, see Prefetch memory.

For information about addressing modes, see Load/Store addressing modes.

Encoding: Unsigned offset

313029282726252423222120191817161514131211109876543210
1111100110
sizeVRopcimm12RnRt

PRFM (<target> is one of: L1 : Level 1 cache, encoded in the "Rt<2:1>" field as 0b00. L2 : Level 2 cache, encoded in the "Rt<2:1>" field as 0b01. L3 : Level 3 cache, encoded in the "Rt<2:1>" field as 0b10. SLC : When FEAT_PRFMSLC is implemented, system level cache, encoded in the "Rt<2:1>" field as 0b11. If "Rt<4:3>" is 0b11 (IR), <target> is omitted. <policy> is one of: KEEP : Retained or temporal prefetch, allocated in the cache normally. Encoded in the "Rt<0>" field as 0. STRM : Streaming or non-temporal prefetch, for data that is used only once. Encoded in the "Rt<0>" field as 1. If "Rt<4:3>" is 0b11 (IR), <policy> is omitted. If "Rt<4:3>" is 0b11 (IR), "Rt<2:0>" is 0b000. For more information on these prefetch operations, see x[Prefetch memory](CEGGGIDE). For other encodings of the "Rt" field, use <imm5>." class="text-blue-400 hover:text-yellow-300"><prfop>|#<prfop>." class="text-blue-400 hover:text-yellow-300"><imm5>), [<Xn|SP>{, #<pimm>}]

Decoding algorithm

constant bits(64) offset = LSL(ZeroExtend(imm12, 64), 3);
constant integer n = UInt(Rn);
constant integer t = UInt(Rt);
constant boolean nontemporal = FALSE;
constant boolean tagchecked = FALSE;

Operation

bits(64) address;

constant boolean privileged = PSTATE.EL != EL0;
constant AccessDescriptor accdesc = CreateAccDescGPR(MemOp_PREFETCH, nontemporal, privileged,
                                                     tagchecked);

if n == 31 then
    address = SP[64];
else
    address = X[n, 64];

address = AddressAdd(address, offset, accdesc);

Prefetch(address, t<4:0>);

Explanations

<prfop>: <imm5>: Is the prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.
This syntax is only for encodings that are not accessible using <prfop>.
<Xn|SP>: Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<pimm>: Is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.